Custom Analog IC Layout Engineer

TheCustom Analog IC Layout Engineerdesigns layouts for high-current and high-voltage transistors, regulators as well as related analog blocks. This position ensures optimal current handling, EM reliability, and thermal performance. The Custom Analog IC Layout Engineerspecializes inpower device layoutfor high-performance, high-reliability analog, and mixed-signal integrated circuits. The role is accountable for the physical layout of power transistors, pass devices, high-current drivers, regulators, and related analog circuitry, working closely with circuit designers from concept through tape-out. The ideal candidate has a deep understanding of high-voltage and high-current layout practices, electromigration limits, parasitic reduction, and thermal management in custom ICs.

• Perform custom layout ofpower transistors, high-current regulators, ESD clamps, and other power handling circuitsin CMOS, BCD, or similar processes.
• Collaborate with designers onfloor planningto optimize current paths, thermal dissipation, and area utilization.
• Apply advanced layout techniques formatching, common centroid, and guard rings, as well as wide-metal routing, and current balancing.
• Ensure compliance with foundryDRC, LVS, and ERCrequirements and address design rule issues proactively.
• Minimize parasitic resistance and capacitance in high-current paths for optimal efficiency.
• Supportparasitic extraction, electromigration verification, and thermal analysis.
• Assist inchip-level integrationand contribute to layout reviews with multidisciplinary teams.

• 3+ yearsof industry experience incustom analog IC layout with a focus on power devices.
• Experience with LDMOS, wide-metal routing, guard rings, and advanced matching techniques is preferred.
• Proficiency in Cadence Virtuoso and PVS/Assura.
• Strong understanding ofpower device layout best practices which include EM, thermal impact, HV spacing, and layered interconnect routing.
• Experience with multiple technology nodes, BCD preferred; high-voltage CMOS, or analog process flows.

• Familiarity withhigh-voltage MOSFET layoutandLDMOS structures.
• Experience withDFM techniques, yield improvement, and layout automation/scripting (SKILL, Python).
• Knowledge ofpackaging technologies (solder balls, RDL, CuP) and package-level thermal/electrical constraintsfor power ICs.
• Experience with foundry release processes.
• Bachelor's degree in Electrical Engineering, EET, or equivalent.

• Comprehensive benefits package including medical, dental, and vision insurance.
• Generous Paid Time Off including paid holidays and floating holidays.
• 401(k) employer match on retirement planning.
• Hybrid working schedule for eligible positions.
• Tuition reimbursement on approved programs.
• Flexible and health spending accounts.
• Talent Development program.