Sr. Principal Electrical Engineer - Analog IC

In this impactful role, you will be responsible for circuit analysis, design, verification, and leading the development of analog integrated circuits used in next generation Wi-Fi front-end modules in Silicon, SOI, and Bi-CMOS technologies. Typical circuits to be developed include FETs and BJTs biasing circuits for Tx and Rx applications, low-dropout regulators (LDOs), bandgap circuits, linear and logarithmic RF detectors, over-voltage/over-current protection circuits, positive and negative charge pump circuits, op-amps/OTAs, and a range of closed loop feedback circuits used in integrated RF modules for Wi-Fi applications. Preferred candidate should also have mixed signal and digital integration experience.

To be successful in this role, you should be fully capable of top-level die development, tape-out, and product ownership and have a strong knowledge of design flow, layout parasitic, and ESD best practices. You should have demonstrated experience in driving analog design innovation and best practices throughout the product development process. Additionally, you will be interacting with designers from multiple sites and require good communication and presentation skills.

#LI-DB1

Andover, MA or Ottawa, Canada

* MS degree (minimum) with at least 12 years of experience in analog IC design using Silicon/SOI/Bi-CMOS process.
* Strong knowledge in transistor-level design of standard analog blocks including bandgaps, op-amps, charge pumps, log detectors, regulators, precision current sources, digital drivers and I/O, basic logic synthesis.
* Experience in top-level chip integration of analog blocks and understanding of system level specification and requirements.
* Comprehensive simulation skills in Cadence including PEX, device matching, stability analysis, Monte Carlo, and Corner analysis.
* Understand concept of ESD protection, noise and crosstalk, grounding, design for yield, manufacturability and testability.
* Experience in mixed signal and digital integration.
* Experience in analog layout best practices and familiar with Cadence Virtuoso.
* Understand device physics, transistor-level modeling and general knowledge of IC fabrication in Silicon or CMOS process 180nm or below.
* Knowledgeable in packaging of integrated module IC product and understand concept of packaging parasitic.
* Must possess good communication and presentation skills and the desire to be part of a dynamic team.