Senior Virtual Platform Functional Modeling Engineer

THE ROLE

AMD is building a next-generation distributed multi-node functional modeling environment to enable scalable pre-silicon system validation across future CPU, GPU, AI, and adaptive computing platforms. This technology provides software-executable representations of complex systems before silicon is available, allowing earlier software development, firmware bring-up, platform validation, and architectural exploration.

As a Virtual Platform Functional Modeling Engineer, you will play a key role in defining and delivering the framework, infrastructure, and methodologies that power AMD's virtual platform capabilities. Working at the intersection of architecture, firmware, software, emulation, and validation, you will help develop a scalable environment that integratesprocessors, memory, I/O, and system-level models into distributed simulation platforms. This is a highly visible opportunity to influence the future of pre-silicon validation and accelerate platform readiness across AMD's product portfolio.

THE PERSON

You are a technically curious engineer who enjoys solving complex system-level challenges and turning architectural concepts into practical solutions. You thrive in collaborative environments where cross-functional teamwork is critical to success and are comfortable partnering with engineers across multiple disciplines and geographic locations.

Youpossessstrong analytical and debugging skills, a passion for computer architecture and system design, and the ability to drive technical initiatives from concept through implementation. You embrace continuous learning, communicate effectively with both technical and non-technical stakeholders, and are motivated by building scalable solutions that havebroadimpact across an organization.

KEY RESPONSIBILITIES

• Collaborate with firmware, software, validation, and emulation teams to enhance virtual platform capabilities and enable complex workload execution.

• Define and implement inter-node communication behavior within distributed simulation environments, including message ordering, flow control, protocol state machines, and error handling mechanisms.

• Design and improvesimulationorchestration services, including job scheduling, synchronization, logging, replay, and deterministic execution capabilities.

• Develop model interfaces, adapters, communication frameworks, and platform assembly methodologies that enable scalable system integration.

• Create validation strategies, regression suites, debug infrastructure, trace capabilities, and CI/CD automation to ensure model quality and reliability.

• Partner with architecture, firmware, software, and system validation teams to align virtual platform functionality with product and platform requirements.

• Evaluate commercial, open-source, and internally developed technologies that improve modeling productivity and platform scalability.

• Contribute to technical documentation, knowledge sharing, training, and engagement with industry partners and open-source communities.

PREFERRED EXPERIENCE

• Functional modeling, virtual platform development, simulation frameworks, firmware enablement, or pre-silicon modeling environments.

• Experience using AI-assisted development tools to design, debug,optimize, andmaintaincomplex software frameworks and models.

• Strong C++ software development skills within modeling, systems software, firmware infrastructure, or platform-level environments.

• Experience developing, integrating, orvalidatingfunctional models, device models, virtual platforms, or modeling APIs.

• Knowledge of test planning, regression infrastructure, validation methodologies, and CI/CD automation.

• Understanding ofSoC and platform architecture, including memory hierarchies, coherency mechanisms, CPU/GPU compute architectures, firmware-visible devices, and high-speed interconnects.

• Familiarity with industry protocols and interconnect technologies such as PCIe, CXL, AXI, CHI, ACE, UCIe, HBM, DDR, or related coherency fabrics.

• Experience translating architecture specifications into executable models and validation-ready platform behavior.

• Exposure to virtual platform technologies such asSystemC/TLM-2.0, Arm Fast Models, Simics, QEMU, or similar frameworks.

• Experience with virtual platform validation, platform bring-up, protocol testing, fault injection, or hardware/software co-validation.

• Familiarity with large-scale infrastructure environments, including cloud-based and distributedcomputeplatforms.

• Experienceestablishingreusable modeling methodologies, APIs, debug capabilities, configuration frameworks, or regression automation standards.

ACADEMIC CREDENTIALS

• Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related technical field preferred.

• Master's degree preferred.

This role is not eligible for visa sponsorship.

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