Test Engineer, Terafab

We are building Terafab, a vertically integrated semiconductor factory at an unprecedented scale. The facility houses logic, memory, packaging, test, and lithography mask production under one roof, optimized for rapid iteration and maximum compute density per square foot.

As a Test Engineer, you will own how Terafab's logic and memory products are tested, from first silicon bring-up through high-volume manufacturing. You will partner closely with the logic and memory design teams on Design-for-Test, build the ATE test programs that run every die we ship, and turn silicon test data into the quality, yield, and cost signals that drive the fab forward. This is a ground-level role at one of the most ambitious fab programs in the world.

This position is open across multiple levels. Level and title are based on your experience, skills, and overall qualifications during the interview process.

• Own test methodology and ATE test program development for Terafab logic and memory products, from pilot silicon through high-volume manufacturing
• Partner with logic design teams on Design-for-Test, including scan chains, ATPG, compression, boundary scan, and silicon debug hooks
• Partner with memory design teams on BIST, redundancy allocation, repair algorithms, and retention and endurance test strategy
• Develop and maintain wafer sort and final test programs on modern ATE platforms (Advantest V93000, Teradyne UltraFLEX, or equivalent)
• Lead first-silicon bring-up: characterization, shmoo (Vmin, Fmax, temperature), bin diagnostics, and A0-to-production debug
• Drive test cost reduction through parallel site expansion, test time optimization, and intelligent re-test flows
• Define outlier screening (PAT, IDDQ, VLV) and the quality gates that feed burn-in, reliability, and ship
• Partner with yield and failure analysis teams to convert test fail signatures into process and design feedback
• Build the data pipelines and dashboards (JMP, Python, SQL) for test yield, bin Pareto, and part average testing
• Support test hardware definition and bring-up (probe cards, load boards, DIBs) with vendors and the fab test floor

• Degree in Electrical Engineering, Computer Engineering, Physics, or equivalent experience
• 10+ years of test or product engineering experience at a high-volume logic or memory semiconductor company
• Deep hands-on experience writing test programs on at least one modern ATE platform (Advantest V93000, Teradyne UltraFLEX or J750, or equivalent)
• Working knowledge of DFT techniques for logic (scan, ATPG, compression, boundary scan, MBIST) and memory (march algorithms, BIST, redundancy repair)
• Experience with first silicon bring-up, characterization, and shmoo-based Vmin, Fmax, and retention analysis
• Fluency with ATE pattern formats (STIL, WGL) and strong Python or equivalent scripting for test data analysis
• Familiarity with test cell integration, probe card and load board bring-up, and parallel site scaling
• Experience defining outlier screening (PAT, IDDQ, VLV) and the quality gates that feed burn-in and reliability
• Demonstrated ability to drive alignment across design, product, yield, and operations teams
• Ability to travel internationally (10%)